I. Field
The present invention relates to the field of electronic circuits. More particularly, the present invention relates to analog-to-digital converters.
II. Background Information
Recently there has been a trend in integrating data converters, such as analog-to-digital converters (ADC), with digital Complementary Metal Oxide Semiconductor (CMOS) circuits fabricated by way of digital CMOS processes. Consistent with higher levels of integration, with smaller system size, and with lower system packaging cost, integration of data converters with digital CMOS is desirable. However, problems may arise when ADCs are integrated with digital CMOS circuits. Frequent digital switching, that takes place in the digital CMOS circuits, may cause noise that tends to corrupt performance of the integrated ADC.
Simultaneous switching of many digital devices, at the clock edges characteristic of digital integrated circuits (IC), may create voltage spikes in the power and ground lines as well as inject current into the substrate. While CMOS digital circuits may be substantially immune to the digital switching noise, performance of analog circuits is degraded in the "mixed mode" integrated analog and digital environment.
Conventional high-speed flash ADCs typically use an auto zeroed architecture to reduce offset errors inherent in component mismatch. These auto-zeroed techniques typically require that well-matched linear capacitors be formed using a double polysilicon CMOS process. Because purely digital CMOS processes generally utilize only a single level of polysilicon, it is difficult to obtain highly linear, well-matched capacitors on that digital CMOS process. Typically, high speed flash ADCs use single-ended circuitry. The single-ended circuitry in these conventional flash ADCs make signals susceptible to the injection of digital switching noise. Therefore, there is a problem with ADCs where noise due to digital switching substantially affects the ADCs performance and where component mismatch contributes to offset errors.